1. Field of the Invention
The present invention relates in general to an ESD protection circuit for mixed-voltage input/output (I/O) circuits. In particular, the present invention relates to an ESD protection circuit using substrate triggering.
2. Description of the Related Art
As the capacity and the processing speed of integrated circuits (ICs) has increase, metal-oxide-semiconductor (MOS) transistors on semiconductor chips have become smaller. Most ICs manufactured in the advanced semiconductor processes require low power supplies and output low-voltage signals. Compatibility of ICs is considered an important issue in an integrated system. ICs requiring low power supplies not only need to receive low-voltage signals from other ICs requiring low power supplies, but also high-voltage signals from ICs manufactured in the old semiconductor processes (requiring high power supplies). The high-voltage signals often cause problems in the reliability of MOS transistors designed for low-voltage signals. Therefore, I/O ports of the ICs of low power supplies are especially required to receive high-voltage signals without component damage. An I/O port capable of receiving high-voltage signals and the low-voltage signals is called a mixed-voltage I/O port.
FIG. 1 is a conventional circuit with a mixed-voltage I/O port. The conventional circuit comprises a pulling-down circuit 10 with two NMOS transistors, Na1 and Na2, stacked in series. The gate of the transistor Na1 is coupled to a power line VDD, and the gate of the transistor Na2 is coupled to internal circuits 11. If the voltage at the pad 14 is higher than the power line VDD, the maximum voltage at the point 12 is equal to the voltage of VDD-Vth, where Vth is the threshold voltage of Na1 device. The problem of device reliability caused by high voltages across the gate oxide layer of the transistor Na2 is solved.
When an ESD stress relatively positive to a power line VSS occurs at the pad 14, the ESD stress is released through the snap-back effect of a parasitic NPN bipolar junction transistor (BJT) under the stacked NMOS transistors Na1 and Na2. The parasitic NPN BJT is triggered by junction-breakdown current from the drain to the bulk of the transistor Na1. However, the junction-breakdown voltage between the drain and the bulk of the NMOS transistor is considerably high, resulting in low triggering speed and poor ESD protection.